A Scalable Architecture for Montgomery MultiplicationA. F. Tenca and C. K. KocCryptographic Hardware and Embedded Systems, C. K. Koc and C. Paar, editors, First International Workshop, Worcester, MA, USA, pages 94-108, Springer Verlag, LNCS Nr. 1717, August 12-13, 1999.AbstractThis paper introduces a scalable architecture for the Montgomery multiplication operation. There is no limitation on the maximum number of bits manipulated by the multiplier, and the selection of the word-size can be made according to the available area and/or desired performance. We give a general description of the new architecture, analyze the hardware organization for parallel computation, and discuss design tradeoffs which are useful to identify the best hardware configuration. |